1. Field of the Invention
The present invention relates to drive circuits for display devices. More particularly, the present invention relates to a shift register for driving a liquid crystal display device.
2. Description of the Related Art
Generally, liquid crystal display (LCD) devices control light transmittance characteristics of liquid crystal material in accordance with applied electric fields and are used as displays for televisions and computers. Accordingly, LCD devices typically include an LCD panel having a plurality of liquid crystal cells arranged in a matrix pattern, and a drive circuit to drive the plurality of liquid crystal cells.
The liquid crystal display panel generally includes a plurality of gate lines; a plurality of data lines crossing the plurality of gate lines, wherein the liquid crystal cells are arranged at crossings of the gate and data lines; pixel electrodes connected to respective ones of the data lines; and a common electrode, wherein pixel electrodes and common electrode generate the electric field that controls the light transmittance characteristics of the liquid crystal material. Each liquid crystal cell includes a switching device such as a thin film transistor (TFT) having source and drain terminals that connect respective ones of the pixel electrode to corresponding data lines. Further, each TFT includes a gate terminal that is connected to a corresponding gate line.
The drive circuit generally includes a gate driver for driving the gate lines and a data driver for driving the data lines. The gate driver sequentially applies scan signals to the plurality of gate lines to sequentially drive rows of liquid crystal cells. Whenever a scan signal is applied to a gate line, the data driver simultaneously applies video signals to each of the data lines. Accordingly, the video signals applied by the data driver selectively generate electric fields between each pixel electrode and the common electrode. By generating the electric fields, light transmittance characteristics of liquid crystal material within the liquid crystal cells are controlled to display images.
Within the related art drive circuit, the gate driver uses a shift register to sequentially generate the scan signals while the data driver uses sampling signals generated by the shift register to sequentially sample externally inputted video signals. Generally, the gate driver, the data driver, and the shift register are formed out of polycrystalline silicon material and formed integrally onto the liquid crystal display panel with the plurality of liquid crystal cells.
FIG. 1 schematically illustrates a related art shift register. FIG. 2 illustrates input/output waveforms of the related art shift register shown in FIG. 1.
Referring to FIG. 1, the shift register includes “n” number of stages ST1 to STn, wherein the stages are connected in cascade to the input line of a start pulse signal SP and to three of four clock signals C1 to C4. Referring to FIG. 2, the start pulse signal SP is applied during either each frame or each horizontal period in synchrony with the fourth clock signal C4. The phase of each of the first to fourth clock signals C1 to C4 is sequentially delayed such the fourth clock signal C4 is applied first, followed by the first clock signal C1, followed by the second clock signal C2, followed by the third clock signal C3.
As shown in FIGS. 1 and 2, the first stage ST1 outputs a first output signal SO1 using three clock signals C1, C3, and C4 and the start pulse signal SP. Subsequently, the second to nth stages ST2 to STn output second to nth output signals SO2 to SOn using various combinations of three of the four clock signals C1 to C4 and corresponding output signal SO1 to SOn-1 of the previous stage. As a result, the first to nth stage ST1 to STn of the related art shift register output the first to nth output signals SO1 to SOn, wherein the phase of the first to nth output signals SO1 to SOn is sequentially shifted as shown in FIG. 2. Accordingly, the first to nth output signals SO1 to SOn are applied as scan signals to sequentially drive the gate lines of the liquid crystal display panel. Moreover, the first to nth output signals SO1 to SOn are provided as the sampling signals by which the data driver sequentially samples the externally inputted video signals.
FIG. 3 illustrates a circuit diagram of a first stage ST1 within the related art shift register shown in FIG. 1.
Referring to FIG. 3, the first stage ST1 includes a first controller 32 for controlling a Q node in accordance with the start pulse signal SP and the fourth clock signal C4; a second controller 34 for controlling a QB node in accordance with the start pulse signal SP and the third clock signal C3; and an output buffer part 36 for selecting a first clock signal C1 or a first supply voltage VSS in accordance with a voltage present at the Q and QB nodes.
Accordingly, the first controller 32 includes a first PMOS transistor T1 connected in a diamond configuration to an input line of the start pulse signal SP; a second PMOS transistor T2 connected between the Q node, an input line of the fourth clock signal C4, and the first PMOS transistor T1; a third PMOS transistor T3 connected between the Q node, the QB node, and an input line of the first supply voltage VSS for controlling the Q node in conjunction with a seventh PMOS transistor T7.
The second controller 34 includes a fourth PMOS transistor T4 connected between an input line of a second supply voltage VDD, an input line of the third clock signal C3, and the QB node; and a fifth PMOS transistor T5 connected between the fourth PMOS transistor T4, the input line of the start pulse signal SP, and the input line of the first supply voltage VSS.
The output buffer part 36 includes a sixth PMOS transistor T6 for selecting the first clock signal C1 in accordance with the voltage present at the Q node and for outputting the first clock signal C1 as the first output signal SO1; and a seventh PMOS transistor T7 for selecting the first supply voltage VSS in accordance with the voltage present at the Q node and for outputting the first supply voltage VSS as the first output signal SO1.
The first stage ST1 further includes a first capacitor CB connected between the gate and source terminals of the sixth PMOS transistor T6 (i.e., between the Q node and the output line to which the first output signal SO1 is applied).
Referring back to FIG. 2, the start pulse signal SP and the first to fourth clock signals C1 to C4 are provided as negative voltages with swing voltage between 10V and 25V when they are applied to the shift register, wherein a voltage of 17V represents a low state and a voltage of −8V represents a high state. The first supply voltage VSS applies the low state voltage of 17V to the first stage ST1 while the second supply voltage VDD applies the high state voltage of −8V.
Referring now to FIGS. 2 and 3, during a first period of time, t1, the start pulse signal SP and the fourth clock signal C4 are simultaneously provided in the high state. Accordingly, the first and second PMOS transistors T1 and T2 are turned on to transmit a high state voltage to the Q node. As a result, the sixth PMOS transistor T6, having its gate terminal connected to the Q node, is slowly turned on. Also during the first period of time, t1, the start pulse signal SP turns the fifth PMOS transistor T5 on, wherein the turned-on fifth PMOS transistor T5 transmits the first supply voltage VSS (i.e., the low state voltage) to the QB node. Accordingly, the third and seventh PMOS transistors T3 and T7, having their gate terminals connected to the QB node, are turned off. As a result, the first clock signal C1, provided in the low state and having a voltage of 17V, is outputted as the first output signal SO1 of the first stage ST1 via the turned-on sixth PMOS transistor T6.
During a second period of time, t2, the start pulse signal SP and the fourth clock signal C4 are simultaneously provided in a low state while the first clock signal C1 is provided in a high state. Accordingly, the first and second PMOS transistors T1 and T2 are turned off and the sixth transistor T6 is completely turned on. More specifically, the first capacitor CB and an internal parasitic capacitor Cgs (not shown), defined between a gate and a source terminal of the sixth PMOS transistor T6, induce a bootstrapping phenomenon at the Q node, wherein the Q node is placed in a floating state by the high state voltage of the first clock signal C1. Accordingly, a voltage value present at the floating Q node is higher than the high state of −8V. Since the sixth PMOS transistor T6 is completely turned on, the high state voltage of the first clock signal C1 (i.e., −8V) is charged to the output line of the stage ST1. Accordingly, the output line of the first stage ST1 outputs an output signal SO1 representing a high state.
During a third period of time, t3, the first clock signal C1 is provided in the low state while the second clock signal C2 is provided in the high state. Accordingly, the voltage value present at the floating Q node is lowered back to the high state and the sixth PMOS transistor T6 is maintained in its turned-on state. As a result, the low state voltage (i.e., 17V) of the first clock signal C1 is outputted as the output signal SO1 via the turned-on sixth PMOS transistor T6.
During a fourth period of time, t4, the third clock signal C3 is provided in the high state to turn the fourth PMOS transistor T4 on, thereby applying the second supply voltage VDD (i.e., the high state voltage of −8V) to the QB node. Accordingly, the third and seventh PMOS transistors T3 and T7 are simultaneously turned on. Subsequently, the low state first supply voltage VSS is applied to the Q node via the turned-on third PMOS transistor T3, thereby turning the sixth PMOS transistor T6 off. As a result, the low state first supply voltage VSS is outputted as the output signal SO1 of the first stage ST1 via the turned-on seventh PMOS transistor T7.
During a fifth period of time, t5, only the fourth clock signal C4 is provided in the high state, wherein the second transistor T2 is turned on while the first, fourth, and fifth PMOS transistors T1, T4, and T5 remain turned off. Accordingly, the voltage present at the QB node is maintained in the high state. As a result, the third and seventh PMOS transistors T3 and T7 remain in their turned-on states to output a low state voltage as the output signal SO1 of the first stage ST1.
As shown above, via the start pulse signal SP and three of four clock signals, the output signal SO1 of the related art first stage ST1 has an ideal swing voltage between 10V and 25V. However, if a threshold voltage Vth of the first and seventh PMOS transistors T1 to T7 is excessively low, a leakage current may be generated, causing distortion of the output signal SO1.
More specifically, and with reference to FIG. 4, if the threshold voltage Vth of the first and seventh PMOS transistors T1 to T7 is excessively low, a leakage current is generated during the second period of time, t2, when the voltage value at the Q node is higher than the high state voltage of −8V. More specifically, leakage current is transmitted along a first leakage current path LCP1, through the fourth PMOS transistor T4, and along second leakage current path LCP2, through the third PMOS transistor T3. During the second period of time, t2, the low state voltage present at the QB node is meant to prevent the voltage of the Q node from being altered. However, due to the presence of the first leakage current path LCP1, the voltage present at the QB node deteriorates from the low state (17V) to the high state (−8V). Furhter, the third PMOS transistor T3 is turned on slightly, and the leakage current transmitted along the second leakage current path LCP2 is increased. Accordingly, the voltage present at the Q node deteriorates from a voltage higher than the high state to the low state voltage due to the presence of the second leakage current path LCP2. When the voltage present at the Q node changes, the conductive path between the drain and source electrodes of the sixth PMOS transistor T6 becomes restrained and the voltage value of the high state output signal SO1, outputted by the sixth PMOS transistor T6, deteriorates from −8V to a lower state value of −7.5V (as shown in FIG. 5).
As mentioned above, the output signal SO1 of the related art first stage ST1 is used as start pulse signal of the next stage, ST2. Moreover, the second to nth stages ST2 to STn are constructed similarly as described above with respect to FIGS. 3 and 4. Accordingly, as the output signal SO1 is propagated through the plurality of cascade connections as start pulse signals SP of succeeding stages, the distortion contained therein increases the leakage current within subsequent stages, thereby deteriorating the reliability of the shift register.